1. Field of the Invention
The present invention relates to a semiconductor memory circuit and, more particularly to a dynamic type random access memory (DRAM) fabricated on a semiconductor substrate.
2. Description of the Related Art
Dynamic memory circuits have been widely utilized as large capacity semiconductor memories. The dynamic memory circuit is typically constructed in such a manner that one-transistor type memory cells each composed of one transistor and a capacitor are arranged in a matrix form of rows and columns together with word lines and bit lines arranged in rows and columns, respectively.
According to the conventional techniques, the number of memory cells connected to one bit line increases as the memory capacity increases. Consequently, a stray capacitance of each bit line increases to give rise to various problems. Firstly, the increased stray capacitance increases the time required to charge the bit lines to a power source potential Vcc or to discharge them to a ground potential when sense amplifiers are activated. If the signals on the bit lines are not amplified sufficiently, i.e., if the charging or discharging thereof are not done sufficiently, it becomes impossible to activate a column selection circuit which connects a selected bit line to a common data line because there is the possibility that, when the common data line is connected to the bit line, the electric charge on the common data line enters the bit line to destroy the stored information. As a result, the outputting of data from an output terminal has to be delayed in order to sufficiently charge or discharge the bit lines, and the operation speed of the memory becomes inferior. Secondary, the increased capacitance of the bit lines causes an increase of the charging and discharging currents, which gives rise to the problems of, for example, the floating of the grounding potential, dropping of the power source potential, occurrence of noise between the bit lines and an increase of the power consumption.